The present invention relates to a semiconductor integrated circuit device having a power supply voltage converter.
Recently, various 1 Mb DRAMs (dynamic random-access memories) which have 2 million or more elements each have been made on trial basis. The narrowest element used in these DRAMs has a width of about 1.2 .mu.m. To fabricate 4 Mb DRAMs and 16 Mb DRAMs, it is necessary to form elements having a width of 1 .mu.m or less. In a 4 Mb or 16 Mb DRAM comprising MOS transistors, each MOS transistor must have a channel length of 1 .mu.m or less. MOS transistors having such a short channel length have an insufficient withstand voltage. Their characteristics will be markedly degraded when a high voltage is applied to the transistors. When the power supply voltage of 5 V, which is generally used, is applied to the MOS transistors, the 4 Mb and 16 Mb DRAMs will function unstably and unreliably. To work stably, they must have a voltage converter for converting the output voltage (5 V) of the generally used external power supply to a lower voltage and applying the lower voltage to the MOS transistors.
FIG. 1 is a block diagram of a conventional DRAM containing a power supply voltage converter which has been designed or fabricated for experimental purposes. The voltage converter is formed in a chip 41 and comprises reference voltage generator 42, error signal amplifier 43 and output circuit 44. Error signal amplifier 43 compares reference voltage VR, i.e., the output of generator 42, with internal power supply voltage Vccl, i.e., the output of circuit 44. Amplifier 43 also controls the conductance of output circuit 44 to make Vccl equal to VR. The output voltage (Vccl) of circuit 44 is applied to DRAM circuit 45.
DRAM circuit 45 comprises clock generator 46, peripheral circuits 47 and core circuit 48. Internal power supply voltage Vccl is applied to clock generator 46, peripheral circuits 47 and core circuit 48. RAS (row address strobe) and CAS (column address strobe) are supplied to clock generator 46 from external devices (not shown). Clock generator 46 generates a reference clock .phi., which is supplied to peripheral circuits 47 and core circuit 48. The greatest DC current which the voltage converter can provide can easily be changed or adjusted by changing the design of output circuit 44.
Internal power supply voltage Vccl (i.e., the output of the conventional voltage converter) changes when a peak current abruptly flows through DRAM circuit 45, as is illustrated in FIGS. 2A, 2B and 2C. More precisely, when current Iccl (FIG. 2B) supplied from output circuit 44 to DRAM circuit 45 rapidly increases, voltage Vccl (FIG. 2A) rapidly falls. This adversely influences the operation of DRAM circuit 45 very much.
Were the voltage converter not provided, the clock pulses would be delayed as shown in FIG. 3 when the voltage applied to clock circuit 46 falls. The data of FIG. 3 has been obtained by computer simulation. The solid line represents how much clock pulses are delayed when the impedance of the power supply lines is relatively high, and the broken line shows how the pulses are delayed when the impedance is negligibly low. The delay of clock pulses, if taking place in the DRAM, will not only lengthen the access time of the DRAM but also will narrow the operation margin of the DRAM.
These problems are more prominent in the DRAM (FIG. 1), as can be clearly understood from FIG. 3, though FIG. 3 shows the results of the computer simulation conducted on the assumption that no power supply voltage converters are used. Due to the response delay of the power supply voltage converter, voltage Vccl considerably falls and cannot regain the initial level in a short time. Consequently, clock pulse generator 46 outputs pulses much delayed.
The response characteristics of the power supply voltage converter can be improved by supplying a great current to error signal amplifier 43 to give amplifier 43 a great drive ability. The general technical trend is, however, to reduce the power consumption of integrated circuits to a minimum. Hence, it is undesirable that a large current is supplied to amplifier 43 formed on chip 41 along with DRAM circuit 45.